qcs_sdk.qpu.isa
The architecture family identifier of an InstructionSetArchitecture
.
Value "Full" implies that each node is connected to every other (fully-connected architecture).
Directly return the Python version of the variant discriminant wrapped by this value; i.e., performs the match Family::Variant(x) => x
for every variant constructor in [Family
]
A degree-two logical connection in the quantum processor's architecture.
The existence of an edge in the ISA Architecture
does not necessarily mean that a given 2Q
operation will be available on the edge. This information is conveyed by the presence of the
two node_id
values in instances of Instruction
.
Note that edges are undirected in this model. Thus edge \( (a, b) \) is equivalent to edge \( (b, a) \).
A logical node in the quantum processor's architecture.
The existence of a node in the ISA Architecture
does not necessarily mean that a given 1Q
operation will be available on the node. This information is conveyed by the presence of the
specific node_id
in instances of Instruction
.
Represents the logical underlying architecture of a quantum processor.
The architecture is defined in detail by the nodes and edges that constitute the quantum
processor. This defines the set of all nodes that could be operated upon, and indicates to
some approximation their physical layout. The main purpose of this is to support geometry
calculations that are independent of the available operations, and rendering ISA-based
information. Architecture layouts are defined by the family
, as follows.
The "Aspen" family of quantum processor indicates a 2D planar grid layout of octagon unit
cells. The node_id
in this architecture is computed as \( 100 p_y + 10 p_x + p_u \) where
\( p_y \) is the zero-based Y position in the unit cell grid, \( p_x \) is the zero-based
X position in the unit cell grid, and \( p_u \) is the zero-based position in the octagon
unit cell and always ranges from 0 to 7.
The "Ankaa" architecture is based on a grid topology; having, in "vertical" orientation, qubits numbered starting from 0 at the top-left and increasing from left to right, then top to bottom, so the final qubit is in the bottom-right. Each qubit is connected with a tunable coupler to their direct vertical and horizontal neighbors, producing an edge. Edges are ordered top-left to bottom-right in this orientation as well, with horizontal rows alternating with vertical rows. Ankaa chips are, in vertical orientation, 7 qubits wide and 12 tall. This architecture may also be presented in "landscape" orientation, which is a simple 90-degree clockwise rotation of the vertical orientation.
Note that the operations that are actually available are defined entirely by Operation
instances. The presence of a node or edge in the Architecture
model provides no guarantee
that any 1Q or 2Q operation will be available to users writing QUIL programs.
A measured characteristic of an operation.
The optional ordered list of parameter values used to generate the characteristic. he order matches the parameters in the enclosing operation, and so the lengths of these two lists must match.
The list of architecture node ids for the site where the characteristic is
measured, if that is different from the site of the enclosing operation.
None
if it is the same. The order of this or the enclosing node ids obey
the definition of node symmetry from the enclosing operation.
A parameter to an operation.
A site for an operation, with its site-dependent characteristics.
An operation, with its sites and site-independent characteristics.
The list of site-independent characteristics of this operation.
The list of sites at which this operation can be applied, together with its site-dependent characteristics.
The list of parameters. Each parameter must be uniquely named. May be empty.
The native instruction set architecture (ISA) of a quantum processor, annotated with characteristics.
The operations described by the instructions
field are named by their QUIL instruction name,
while the operation described by the benchmarks
field are named by their benchmark routine
and are a future extension point.
The characteristics that annotate both instructions and benchmarks assist the user to generate the best native QUIL program for a desired task, and so are provided as part of the native ISA.
Deserialize an InstructionSetArchitecture
from a json representation.
Parameters
- value: The json-serialized
InstructionSetArchitecture
to deserialize.
Raises
- SerializeISAError: If the input string was not deserialized correctly.
Serialize the InstructionSetArchitecture
to a json string, optionally pretty-printed.
Parameters
- pretty: If the json output should be pretty-printed with newlines and indents.
Raises
- SerializeISAError: If the input string was not serialized correctly.
The list of native QUIL instructions supported by the quantum processor.
If an InstructionSetArchitecture
could not be serialized or deserialized correctly.
If there was an issue fetching InstructionSetArchitecture
from the QCS API.
Fetch the InstructionSetArchitecture
(ISA) for a given quantum_processor_id
from the QCS API.
Parameters
- quantum_processor_id: The ID of the quantum processor
- client: The
QCSClient
to use. Creates one using environment configuration if unset - see https: //docs.rigetti.com/qcs/references/qcs-client-configuration
Raises
- LoadClientError: If
client
was not provided to the function, and failed to load internally. - GetISAError: If there was an issue fetching the ISA from the QCS API.
Fetch the InstructionSetArchitecture
(ISA) for a given quantum_processor_id
from the QCS API.
(async analog of get_instruction_set_architecture
)
Parameters
- quantum_processor_id: The ID of the quantum processor
- client: The
QCSClient
to use. Creates one using environment configuration if unset - see https: //docs.rigetti.com/qcs/references/qcs-client-configuration
Raises
- LoadClientError: If
client
was not provided to the function, and failed to load internally. - GetISAError: If there was an issue fetching the ISA from the QCS API.